IA186EM_04 Datasheet, PDF (63/133 Pages) InnovASIC, Inc – 8/16-Bit Microcontrollers

IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
hold – Bus Hold Request (synchronous level-sensitive input)
This pin is pulled high to signal the microcontroller that the system requires control of the local bus.
hold latency time (time between the hold and hlda) depends on the current processor activity when the
hold is received. A hold request is second only do a DMA refresh request in priority of processor activity
requests. If a hold request is received at the moment a DMA transfer starts, the hold latency can be up to
4 bus cycles. (On the IA186EM only, this happens when a word transfer is taking place from an odd to an
odd address). This means that the latency may be 16 clock cycles without wait states. Furthermore, if
lock transfers are being performed, then the latency time is increased by the during of the locked transfer.
int0 – Maskable Interrupt Request 0 (asynchronous input)
The int0 pin provides an indication that an interrupt request has occurred, and provided that int0 is not
masked, program execution will continue at the location specified by the INT0 vector in the interrupt
vector table. Although interrupt requests are asynchronous, they are synchronized internally and may be
edge- or level-triggered. The assertion of the interrupt request must be maintained until it is handled, to
ensure that it is recognized.
int1/select_n – Maskable Interrupt Request 1/Slave Select (both are asynchronous inputs)
int1 - The int1 pin provides an indication that an interrupt request has occurred, and provided that int1 is
not masked, program execution will continue at the location specified by the INT1 vector in the interrupt
vector table. Although interrupt requests are asynchronous, they are synchronized internally and may be
edge- or level-triggered. The assertion of the interrupt request must be maintained until it is handled, to
ensure that it is recognized.
select_n – This pin provides an indication to the microcontroller that an interrupt type has been placed on
the address/data bus when the internal Interrupt Control Unit is slaved to an external interrupt controller.
Before this occurs, however, the int0 pin must have indicated an interrupt request has occurred.
int2/inta0_n (pio31) – Maskable Interrupt Request 2 (asynchronous input) / Interrupt Acknowledge
0 (synchronous output)
int2 - The int2 pin provides an indication that an interrupt request has occurred, and provided that int2 is
not masked, program execution will continue at the location specified by the int2 vector in the interrupt
vector table. Although interrupt requests are asynchronous, they are synchronized internally and may be
edge- or level-triggered. The assertion of the interrupt request must be maintained until it is handled, to
ensure that it is recognized. When int0 is configured to be in cascade mode, int2 changes its function to
inta0_n.
inta0_n – this function indicates to the system that the microcontroller requires an interrupt type in
response to the interrupt request int0 when the microcontroller’s Interrupt Control Unit is in cascade
mode. The peripheral device that issued the interrupt must provide the interrupt type.
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