IA186EM_04 Datasheet, PDF (22/133 Pages) InnovASIC, Inc – 8/16-Bit Microcontrollers

IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
The value in this register determines the number of internal processor cycles in one phase (half-period) of
the 32 x serial clock.
The contents of these registers must be adjusted to reflect the new processor clock frequency if power-
save mode is in effect.
The baud rate divisor may be calculated from:
BAUDDIV = (Processor Frequency / (32 x baud rate)) -1
By setting the BAUDDIV to 0000h, the maximum baud rate of 1/32 of the internal processor frequency
clock is set. Setting BAUDDIV to 129 (81h) provides a baud rate of 9600 at 40MHz. The baud rate
tolerance is +4.6% and –1.9% with respect to the actual serial port baud rate, not the target baud rate.
Baud Rates
Baud Rate
300
600
1200
2400
4800
9600
14400
19200
625 Kbaud
781.25 Kbaud
1.041 Mbaud
1.25 Mbaud
20 MHz
2082
1040
519
259
129
64
42
31
0
n/a
n/a
n/a
Divisor Based on CPU Clock Rate
25 MHz
33 MHz
2603
3471
1301
1735
650
867
324
433
161
216
80
107
53
71
39
53
n/a
n/a
0
n/a
n/a
0
n/a
n/a
40 MHz
4165
2082
1040
519
259
129
85
64
1
n/a
n/a
0
The value of the SPBAUD register at reset is undefined.
15
14
13 12 11 10 9
BAUDDIV
8 76543 2 1 0
BAUDDIV [15:0] (bits 15-0) – Baud Rate Divisor. Defines the divisor for the internal processor
clock.
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