IA186EM_04 Datasheet, PDF (21/133 Pages) InnovASIC, Inc – 8/16-Bit Microcontrollers

IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
active state at reset with a memory range of 64 Kbytes (F0000h to FFFFFh), external ready required, and
three wait states automatically inserted. The upper end of the memory range always ends at FFFFFh,
whereas the lower end of this upper memory range is programmable.
The value of the UMCS register is F03Bh at reset.
15 14
13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
LB2 – LB0
0 0 0 0 DA 0 1 1 1 R2 R1-R0
Reserved [15] (bit 15) – Set to 1.
LB [2:0] (bits 14–12) – Lower Boundary. These bits determine the bottom of the memory accessed
by the ucs_n chip selects.
UMCS Block Size Programming Values
Memory
Block
Size
64K
128K
256K
512K
Starting
Address
F0000h
E0000h
C0000h
80000h
LB2 – LB0
111b
110b
100b
000b
Comments
Default
Reserved (bits 11 – 8)
DA (bit 7) – Disable Address. When set to 0, the address is driven onto the address bus (ad15 – ad0)
during the address phase of a bus cycle when ucs_n is asserted. If DA is set to 1, the address bus is
disabled, and the address is not driven on the address bus when ucs_n is asserted, providing some
measure of power saving. This bit is set to 0 at reset.
If bhe_n/aden_n is held at 0 during the rising edge of res_n, then the address bus is always driven
independent of the setting of DA.
Reserved (bit 6) – Set to 0.
Reserved (bit 5 – 3) – Set to 1.
R2 (bit 2) Ready Mode – When this bit is set to 0, an external ready is required. But when set to 1, the
external ready is ignored. In either case, however, the value of the R1 - R0 bits determine the number
of wait states inserted.
R [1:0] (bits 1-0) - Wait-State Value. The number of wait states inserted into an access to the lcs_n
memory area is determined by the value of these bits. This number ranges from 0 to 3 (R1 – R0 = 00b
to 11b).
SPBAUD (088h) - Serial Port BAUD Rate Divisor Register.
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