IA186EM_04 Datasheet, PDF (36/133 Pages) InnovASIC, Inc – 8/16-Bit Microcontrollers

IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
C (bit 5) – Cascade Mode. This bit enables cascade mode for int0 or int1 when set to 1.
LTM (bit 4) – Level-Triggered Mode. The int0 or int1 interrupt may be edge or level triggered
depending on the value of the bit. If LTM is 1, int0 or int1 is an active high level-sensitive interrupt.
If LTM is 0, int0 or int1 is a rising edge triggered interrupt. The interrupt int0 or int1 must remain
active (high) until acknowledged.
MSK (bit 3) – Mask. The int0 or int1 signal can cause an interrupt if the MSK bit is 0. The int0 or
int1 signal cannot cause an interrupt if the MSK bit is 1. The Interrupt Mask Register has a duplicate
of this bit.
PR2-PR0 (bit 2-0) – Priority. These bits define the priority of the serial port interrupt int0 or int1 in
relation to other interrupt signals. The interrupt priority is the lowest at 7 at reset. The values of PR2
– PR0 are shown in the above table (Priority Level).
TCUCON (032h) - Timer Control Unit Interrupt CONtrol Register.
Master Mode
The three timers have their interrupts assigned to types 08h, 12h, and 13h and are configured by this
register.
The value of this register is 000Fh at reset.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
MSK PR2-PR0
Reserved (bits 15-4) – Set to 0.
MSK (bit 3) – Interrupt Mask. An interrupt source may cause an interrupt if the MSK bit is 0. The
interrupt source cannot cause an interrupt if the MSK bit is 1. The Interrupt Mask Register has a
duplicate of this bit.
PR2-PR0 (bit 2-0) – Priority. These bits define the priority of the serial port interrupt in relation to
other interrupt signals. The interrupt priority is the lowest at 7 at reset. The values of PR2 – PR0 are
shown in the above table (Priority Level).
T2INTCON (03ah) - Timer INTerrupt CONtrol Register.
T1INTCON (038h)
T0INTCON (032h)
Slave Mode
The three timers, Timer2, Timer1, and Timer0, each have an interrupt control register, whereas in master
mode all three are masked and prioritized in one register (TCUCON).
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