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IA186EM_04 Datasheet, PDF (94/133 Pages) InnovASIC, Inc – 8/16-Bit Microcontrollers
IA186EM/IA188EM
8/16-BIT Microcontrollers
Waveforms
Data Sheet
As of Production Version -03
Alphabetic Key to Waveform Parameters
No. Name Description
No. Name Description
49 tARYCH ardy Resolution Transition Setup Time 2 tCLDX Data in Hold
51 tARYCHL ardy Inactive Holding Time
71 tCLEV clkoutA Low to sden Valid
52 tARYLCL ardy Setup Time
62 tCLHAV hlda Valid Delay
87 tAVBL a Address Valid to whb_n/wlb_n Low 82 tCLRF clkoutA High to rfsh_n Invalid
14 tAVCH ad Address Valid to Clock High
27 tCLRH rd_n Inactive Delay
12 tAVLL ad Address Valid to ale Low
25 tCLRL rd_n Active Delay
66 tAVRL a Address Valid to rd_n Low
4 tCLSH Status Inactive Delay
65 tAVWL a Address Valid to wr_n Low
72 tCLSL clkoutA Low to sclk Low
24 tAZRL ad Address Float to rd_n Active
48 tCLSRY srdy Transistion Hold Time
45 tCH1CH2 clkoutA Rise Time
55 tCLTMV Timer Output Delay
68 tCHAV clkoutA High to A Address Valid
83 tCOAOB clkoutA to clkoutB Skew
38 tCHCK X1 High Time
20 tCVCTV Control Active Delay 1
44 tCHCL clkoutA High Time
31 tCVCTX Control Inactive Delay
67 tCHCSV clkoutA High to lcs_n/usc_n Valid
21 tCVDEX den_n Inactive Delay
18 tCHCSX mcs_n/pcs_n Inactive Delay
17 tCXCSX mcs_n/pcs_n Hold from Command Inactive
22 tCHCTV Control Active Delay 2
1 tDVCL Data in Setup
64 tCHCV Command Lines Valid Delay (after Float) 75 tDVSH Data Valid to SCLK High
63 tCHCZ Command Lines Float Delay
19 tDXDL den_n Inactive to dt_r_n Low
8 tCHDX Status Hold Time
58 tHVCL hld Setup Time
9 tCHLH ale Active Delay
53 tINVCH Peripheral Setup Time
11 tCHLL ale Inactive Delay
54 tINVCL drq Setup Time
79 tCHRFD clkoutA High to rfsh_n Valid
86 tLCRF lcs_n Inactive to rfsh_n Active Delay
3 tCHSV Status Active Delay
23 tLHAV ale High to Address Valid
69 tCICOA X1 to clkoutA Skew
10 tLHLL ale Width
70 tCICOB X1 to clkoutB Skew
13 tLLAX ad Address Hold from ALE Inactive
39 tCKHL X1 Fall Time
61 tLOCK Maximum PLL Lock Time
36 tCKIN X1 Period
84 tLRLL lcs_n Precharge Pulse Width
40 tCKLH X1 Rise time
57 tRESIN res_n Setup Time
46 tCL2CL1 clkoutA Fall Time
85 tRFCY rfsh_n Cycle Time
50 tCLARX ardy Active Hold Time
29 tRHAV rd_n Inactive to ad Address Active
5 tCLAV ad Address Valid Delay
59 tRHDX rd_n High to Data Hold on ad Bus
6 tCLAX Address Hold
28 tRHLH rd_n Inactive to ale High
15 tCLAZ ad Address Float Delay
26 tRLRH rd_n Pulse Width
43 tCLCH clkoutA Low Time
77 tSHDX sclk High to SPI Data Hold
37 tCLCK X1 Low Time
78 tSLDV sclk Low SPI Data Hold
42 tCLCL clkoutA Period
47 tSRYCL srdy Transition Setup Time
80 tCLCLX lcs_n Inactive Delay
35 tWHDEX wr_n Inactive to den_n Inactive
81 tCLCSL lcs_n Active Delay
34 tWHDX Data Hold after wr_n
16 tCLCSV mcs_n/pcs_n Inactive Delay
33 tWHLH wr_n Inactive to ale High
30 tCLDOX Data Hold Time
32 tWLWH wr_n Pulse Width
7 tCLDV Data Valid Delay
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