IA186EM_04 Datasheet, PDF (19/133 Pages) InnovASIC, Inc – 8/16-Bit Microcontrollers

IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
PCS Address Ranges
PCSn Line
PCS0n
PCS1n
PCS2n
PCS3n
Reserved
PCS5n
PCS6n
Range
Low
High
Base Address
Base Address + 255
Base Address + 256 Base Address + 511
Base Address + 512 Base Address + 767
Base Address + 768 Base Address + 1023
N/A
N/A
Base Address + 1280 Base Address
Base Address + 1536 Base Address
Reserved [6:4] (bits 6-4) – Set to 1.
R [3] (bit 3) – Wait State Value. See the following table.
R [2] (bit 2) – Ready Mode. When 0, external ready is required. When 1, external ready is ignored.
But in each case the number of wait states is determined as in the following table.
R [1:0] (bits 1 – 0) – Wait-State Value. See following table. It should be noted that pcs6_n – pcs5_n
and pcs3_n – pcs0_n pins are multiplexed with the programmable I/O pins. And for them to function
as chip selects, the PIO mode and direction settings for these pins must be set to 0 for normal
operation.
PCS3n – PCS0n Wait–State Encoding
R3
R1
R0
Wait States
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
5
1
0
1
7
1
1
0
9
1
1
1
15
LMCS (0a2h) - Low Memory Chip Select Register configures the Low Memory Chip Select that has
been provided to facilitate access to the interrupt vector table located at 00000h or the bottom of memory.
The lcs_n pin is not active at reset.
The width of the data bus for the lcs_n space should be configured in the AUXCON register before
activating the lcs_n chip select pin, by any write access to the LMCS register.
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel [phone] • Fax [phone] • www.Innovasic.com