IA186EM_04 Datasheet, PDF (49/133 Pages) InnovASIC, Inc – 8/16-Bit Microcontrollers

IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
Clock and Power Management
A phase-lock-loop (PLL) and a second programmable system clock output (CLKOUTB) are included in
the clock and power management unit. The internal clock is the same frequency as the crystal but with a
duty cycle of 45% - 55 %, as a worse case, generated by the PLL obviating the need for an x2 external
clock. A power-on reset (POR) resets the PLL.
C₁
X1
Recommended range of
values for C₁ and C₂ are:
X2
C₂
Crystal
Am186/188EM
C_{1 =} 15pF +/- 20%
C_{2 =} 22pF +/- 20%
Figure 2. Crystal Configuration
System Clocks
If required, the internal oscillator can be driven by an external clock source that should be connected to
X1, leaving X2 unconnected.
The clock outputs clkouta and clkoutb may be enabled or disabled individually (Power-Save Control
register (PDCON) bits (11 – 8)). These clock control bits allow one clock output to run at PLL frequency
and the other to run at the power-save frequency.
PLL
X1,
X2
Power-Save
Divisor
(/2 to /128)
Processor Internal Clock
Mux
Drive enable
Time
Mux
Delay
6 +/- 2.5nS
clkouta
clkoutb
Drive enable
Figure 3. Organization of Clock
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel [phone] • Fax [phone] • www.Innovasic.com