IA186EM_04 Datasheet, PDF (57/133 Pages) InnovASIC, Inc – 8/16-Bit Microcontrollers

IA186EM/IA188EM
8/16-BIT Microcontrollers
20-bit Adder/Subtractor
20
Transfer Counter Ch. 1
Destination Address Ch. 1
Source Address Ch. 1
Transfer Counter Ch. 0
Destination Address Ch. 0
Source Address Ch. 0
Data Sheet
As of Production Version -03
Adder Control
Logic
DMA
Control
Logic
Timer Request
Request
Selection
Logic
drq1
drq0
Interrupt
Request
Channel Control Register 1
20
Channel Control Register 0
16
Internal Address/Data Bus
Figure 4. DMA Unit
DMA Priority
DMA transfers have a higher priority than CPU transfers, with the exception of word accesses to odd
memory locations or between locked memory addresses. The CPU cannot access memory during a DMA
transfer and a DMA transfer cannot be suspended by an interrupt request. Continuous DMA activity will
thus cause interrupt latency to suffer. However, an NMI request halts any DMA activity, enabling the
CPU to respond promptly to the request.
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