IA186EM_04 Datasheet, PDF (130/133 Pages) InnovASIC, Inc – 8/16-Bit Microcontrollers

IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
Analysis: The string of DMA transfers is ended by writing x0004 to PCB address xCA or xDA while
DMA request line is asserted. By this time, the sequence to initiate the DMA transfer cannot be
suppressed or recalled, so the IA device executes the spurious transfer.
Workaround: None.
5) Problem: In the 186/188ES devices, the TB8 bit of the UART control register (offset x10 or x80) does not
automatically reset after transmitting the initial word when using 9-bit formats (modes 2 or 3).
Analysis: This feature is used to designate the “address” byte when using the UART in a psuedo-
LAN configuration. The automatic reset of TB8 allows a convenient means to send a block of words
with little software interaction.
Workaround: Manually reset TB8 after detecting the end of the first transmitted word.
6) Problem: In the 186/188ES devices, the Power Save clock speed is not working correctly.
Analysis: A logic error causes the device to incorrectly clear bits [2:0] of the PDCON when the
device leaves power save mode by clearing bit 15 of the PDCON.
Workaround: Every time the programmer desires to go into power save mode by setting bit 15 of the PDCON
register, then bits [2:0] should also be set according to the desired clock divide factor. It should not be assumed
that once written to, bits [2:0] will retain their values when entering and exiting the power save mode.
7) Problem: The device responds incorrectly to false start bits.
Analysis: If a start bit is less than half width, the device should ignore this start bit completely (no
data byte, no errors). Instead the device treats the data that follows as a valid byte, and generates a
framing error.
Workaround: Eliminate false start bits, or revise how the resulting framing error and extra byte are handled.
8) Problem: The UART is disabled when an external system generates a break condition.
Analysis: The device should not be disabled when an external system generates a break condition,
instead once the break condition is deasserted the UART should start receiving data. However, the
UART in the Innovasic device is disabled by the externally generated break condition and can only
receive data once the break flags (Bit 9: BRK0 of registers SP0ST and/or SP1ST) are cleared.
Workaround: Ensure that every time an external break condition is acknowledged, that the break flag bits are
cleared.
9) Problem: The MOV instruction does work when an attempt is made to load the CS register.
Analysis: On the OEM AMD part a MOV CS, AX command loads CS with the contents of AX. The
Innovasic part never loads CS with AX by use of a MOV instruction.
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel [phone] • Fax [phone] • www.Innovasic.com