IA186EM_04 Datasheet, PDF (85/133 Pages) InnovASIC, Inc – 8/16-Bit Microcontrollers

IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
Instruction
Mnemonic
Description
AND imm8 with AL
AND imm16 with AX
AND imm8 with r/m8
TEST
AND imm16 with r/m16
AND byte reg with r/m8
AND word reg with r/m16
WAIT
XCHG
XLAT
XLATB
Performs a NOP
Exchange word reg with AX
Exchange AX with word reg
Exchange byte reg with r/byte
Exchange r/m8 with byte reg
Exchange word reg with r/m16
Exchange r/m16 with word reg
Set AL to memory byte segment
:[BX+unsigned AL]
Set AL to memory byte DS
:[BX+unsigned AL]
XOR imm8 with AL
XOR imm16 with AX
XOR imm8 with r/m8
XOR ^{XOR imm16 with r/m16}
XOR sign-extended imm8 with
r/m16
XOR byte reg with r/m8
XOR word reg with r/m16
XOR r/m8 with byte reg
XOR r/m16 with word reg
Opcode - Hex
byte byte byte
1 2 3-6
A8 ib -
A9 iw -
F6
/0 data
ib 8
F7
/0
iw
-
84 /r -
85
/r
data
8
9B - -
90 - -
+rw - -
86 - -
/r - -
87 - -
/r - -
D7 - -
D7 - -
34 ib -
35 iw -
80
/6
ib
-
81
/6
iw
-
83
/6
ib
-
30 /r -
31 /r -
32 /r -
33 /r -
Clock Cycles
IA186 IA188
3
3
4
4
4/10 4/10
4/10 4/14
3/10 3/10
3/10 3/14
-
-
3
3
3
3
4/17 4/17
4/17 4/17
4/17 4/21
4/17 4/21
11
15
11
15
3
3
4
4
4/16 4/16
4/16 4/20
4/16 4/20
3/10 3/10
3/10 3/14
3/10 3/10
3/10 3/14
Flags Affected
ODI TSZ APC
0 - - - RRUR 0
-------- -
-------- -
-------- -
0 - - - RRUR 0
Key to Abbreviations Used Instruction Summary Table
The Operand Address byte is configured as follows.
7
6
5
4
3
mod field
aux field
2
1
0
r/m field
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