IA186EM_04 Datasheet, PDF (38/133 Pages) InnovASIC, Inc – 8/16-Bit Microcontrollers

IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
The value of these registers is 000Fh at reset.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
MSK PR2 - PR0
Reserved (bits 15-4) – Set to 0.
MSK (bit 3) – Mask. Any of the interrupt sources may cause an interrupt if the MSK bit is 0. The
interrupt sources cannot cause an interrupt if the MSK bit is 1. The Interrupt Mask Register has a
duplicate of this bit.
PR2-PR0 (bits 2-0) – Priority. These bits define the priority of the serial port interrupts in relation to
other interrupt signals. The interrupt priority is the lowest at 7 at reset. The values of PR2 – PR0 are
shown in the above table (Priority Level).
INTSTS (030h) – INTerrupt STatuS Register.
Master Mode
The Interrupt status register contains the interrupt request status of each of the three timers, Timer2,
Timer1, and Timer0.
15 14 13 12 11 10 9 8 7 6 5 4 3 2
1
0
DHLT
Reserved
TMR2 - TMR0
DHLT (bit 15) – DMA Halt. DMA activity is halted when this bit is 1. It is set to 1 automatically
when any non-maskable interrupt occurs and is cleared to 0 when an IRET instruction is executed.
Interrupt handlers and other time critical software may modify this bit directly to disable DMA
transfers. However, the DHLT bit should not be modified by software if the timer interrupts are
enabled as the function of this register as an interrupt request register for the timers would be
compromised.
Reserved (bits 14-3)
TMR [2:0] (bit 2-0) – Timer Interrupt Request. A pending interrupt request is indicated by the
respective timer, when any of these bits is 1. (N.B. the TMR bit in the REQST register is a logical OR
of these timer interrupt requests)
Slave Mode
When nonmaskable interrupts occur the interrupt status register controls DMA operation and the interrupt
request status of each of the three timers, Timer2, Timer1, and Timer0.
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