IA186EM_04 Datasheet, PDF (34/133 Pages) InnovASIC, Inc – 8/16-Bit Microcontrollers

IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
These registers control the operation of the Watchdog Timer interrupt source. The value of this register is
000Fh at reset.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Res MSK
PR2-PR0
Reserved (bits 15-5) – Set to 0.
Reserved (bit 4) – Set to 0.
MSK (bit 3) – Mask. This bit, when 0, enables the Watchdog Timer to cause an interrupt. When this
bit is 1 prevents the Watchdog Timer from generating an interrupt.
PR2-PR0 (bits 2-0) – Priority. These bits define the priority of the Watchdog Timer interrupt in
relation to other interrupt signals. The interrupt priority is the lowest at 7 at reset. The values of PR2
– PR0 are shown in the above table (Priority Level).
I4CON (040h) – INT4 CONtrol Register.
Master Mode
This register controls the operation of the int4 signal, which is only intended for use in fully nested mode.
The interrupt is assigned to type 10h.
The value of the I4CON register is 000Fh at reset.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
LTM MSK PR2-PR0
Reserved (bits 15-5) – Set to 0.
LTM (bit 4) – Level-Triggered Mode. The int4 interrupt may be edge or level triggered depending on
the value of the bit. If LTM is 1, int4 is active high-level sensitive interrupt l. If LTM is 0, int4 is a
rising edge triggered interrupt. The interrupt int4 must remain active (high) until serviced.
MSK (bit 3) – Mask. The int4 signal can cause an interrupt if the MSK bit is 0. The int4 signal cannot
cause an interrupt if the MSK bit is 1.
PR2-PR0 (bit 2-0) – Priority. These bits define the priority of the serial port interrupt in relation to
other interrupt signals. The interrupt priority is the lowest at 7 at reset. The values of PR2 – PR0 are
shown in the above table (Priority Level).
I3CON (03eh) – INT2/INT3 CONtrol Register.
I2CON (03ch),
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