IA186EM_04 Datasheet, PDF (43/133 Pages) InnovASIC, Inc – 8/16-Bit Microcontrollers

IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
WD (bit 9) – Watchdog Timer Interrupt In-Service Request. Setting this bit to 1 is an indication that
the Watchdog Timer interrupt is masked.
I [4:0] (bits 8 - 4) Interrupt Mask. Setting any of these bits to 1 is an indication that the relevant
interrupt is masked.
D1-D0 (bit 3:2) DMA Channel Interrupt Mask. Setting this bit to 1 is an indication that the respective
DMA channel interrupt is masked.
Reserved (bit 1)
TMR (bit 0) – Timer Interrupt Mask. When set to 1, it indicates that the timer control unit interrupt is
masked.
Slave Mode
The interrupt mask register is read/write. Setting a bit in this register is effectively the same as setting the
MSK bit in the corresponding interrupt control register. Setting a bit to 1 masks the interrupt request. The
interrupt request is enabled when the corresponding bit is set to 0.
The IMASK register contains 003dh on reset.
15 14 13 12 11 10 9 8 7 6 5
4 321 0
Reserved
TMR2 TMR1 D1 D0 Res TMR0
Reserved (bits 15 – 6)
TMR2 (bit 5) Timer2 Interrupt Mask. This bit provides an indication of the state of the mask bit in
the Timer Interrupt Control register. When it is set to 1, it indicates that the interrupt request is
masked.
TMR1 (bit 4) Timer1 Interrupt Mask. This bit provides an indication of the state of the mask bit in
the Timer Interrupt Control register. When it is set to 1, it indicates that the interrupt request is
masked.
D1-D0 (bit 3:2) DMA Channel Interrupt Mask. This bit provides an indication of the state of the
mask bit in the respective DMA channel Interrupt Control register. When it is set to 1, it indicates that
the interrupt request is masked.
Reserved (bit 1)
TMR0 (bit 0) – Timer Interrupt Mask. This bit provides an indication of the state of the mask bit in
the Timer Interrupt Control register. When it is set to 1, it indicates that the interrupt request is
masked.
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