IA186EM_04 Datasheet, PDF (65/133 Pages) InnovASIC, Inc – 8/16-Bit Microcontrollers

IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
mcs3_n/rfsh_n (pio25) – Midrange Memory Chip Select (synchronous output with internal pull-up)
/ Automatic Refresh (synchronous output)
mcs3_n - The mcs3_n pin provides an indication that a memory access is in train to the fourth region of
the midrange memory block. The size of the Midrange Memory Block and its base address are
programmable. mcs3_n is held high during bus hold and has a weak pull-up that is present only during
reset.
rfsh_n – This signal is timed for auto refresh to PSRAM or DRAM devices. The refresh pulse is output
only when the PSRAM or DRAM mode bit is set (EDRAM register bit 15). This pulse is of 1.5 clock
pulse duration with the rest of the refresh cycle made up of a deassertion period such that the overall
refresh time is met. Finally, this pin is not tristated during a bus hold.
nmi – Nonmaskable Interrupt (synchronous edge-sensitive input)
This is the highest priority interrupt signal and cannot be masked, unlike int4 – int0.
Program execution is transferred to the nonmaskable interrupt vector in the interrupt vector table, upon
the assertion of this interrupt (transition from Low to High), and this interrupt is initiated at the next
instruction boundary. For recognition to be assured the nmi pin must be held high for at least a clkouta
period so that the transition from low to high is latched and synchronized internally. The interrupt will
begin at the next instruction boundary.
The NMI is not involved in the priority resolution process that deals with the maskable interrupts, and
does not have an associated interrupt flag. This allows for a new NMI request to interrupt an NMI service
routine that is already underway. The interrupt flag IF is cleared, disabling the maskable interrupts, when
an interrupt is taken by the processor. If, during the NMI service routine, the maskable interrupts are re-
enabled, by use of STI instruction for example, the priority resolution of maskable interrupts will be
unaffected by the servicing of the NMI. For this reason, it is strongly recommended that the NMI interrupt
service routine does not enable the maskable interrupts.
pcs3_n - pcs0_n (pio19 – pio16) – Peripheral Chip Selects 3-0 (synchronous outputs)
These pins provide an indication that a memory access is under way for the corresponding region of the
peripheral memory block (I/O or memory address space). The base address of the Peripheral memory
block is programmable. pcs3_n – pcs0_n are held high during both bus hold and reset. These outputs are
asserted with the ad address bus over a 256-byte range each.
pcs5_n/A1– Peripheral Chip Select 5 (synchronous output) / latched Address Bit 1 (synchronous
output)
pcs5_n – This signal provides an indication that a memory access is under way for the sixth region of the
peripheral memory block (I/O or memory address space). The base address of the Peripheral memory
block is programmable. pcs5_n is held high during both bus hold and reset. This output is asserted with
the ad address bus over a 256-byte range.
A1 – This pin provides and internally latched address bit 1 to the system when the EX bit (bit 7) in the
MCS_n and PCS_n auxiliary (MPCS) register is 0. It retains its previously latched value during a bus
hold.
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