IA186EM_04 Datasheet, PDF (10/133 Pages) InnovASIC, Inc – 8/16-Bit Microcontrollers

IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
PRL Value
01h
02h
03h
04h
Processor Release Level
C
D
E
F
RES (bits 7-0) – Reserved.
PDCON (0f0h) - The Power-save CONtrol Register controls several miscellaneous system I/O and
timing functions.
The SYSCON contains 0000h at reset.
15
14
13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSEN
RES
CBF CBD CAF CAD
RES
F2 F1 F0
PSEN (bit 15) – When set to 1, enables the power-save mode causing the internal operating clock to
be divided by the value in F2-F0. External interrupts or interrupts from internal interrupts
automatically clear PSEN. Software interrupts and exception do not clear PSEN. Note that the value of
PSEN is not restored upon execution of an IRET instruction.
RES (bit 14-12) – Reserved. These bits read back as zeros.
CBF (bit 11) – When set to 1, the clkoutb output follows the input crystal (PLL) frequency. When
this bit is 0, the clkoutb follows the internal clock frequency after the clock divider.
CBD (bit 10) – When set to 1, the clkoutb output is pulled low. When this bit is 0, the clkoutb is
driven as an output per the CBF bit.
CAF (bit 9) – When set to 1, the clkouta output follows the input crystal (PLL) frequency. When this
bit is 0, the clkouta follows the internal clock frequency after the clock divider.
CAD (bit 8) – When set to 1, the clkouta output is pulled low. When this bit is 0, the clkouta is driven
as an output per the CBF bit.
RES (bits 7-3) – Reserved. These bits read back as zeros.
F2-F0 (bits 2-0) – These bits control the clock divider as shown below. Note that PSEN must be 1 for
the clock divider to function.
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