IA186EM_04 Datasheet, PDF (47/133 Pages) InnovASIC, Inc – 8/16-Bit Microcontrollers

IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
This register controls the operation of the sden1 and sden0 outputs and the baud rate of the SSI port. The
sden1 and sden0 outputs are held high when the respective bit is set to 1, but in the event that both DE1
and DE0 are set to 1 then only sden0 will be held high.
The value of the SSR register is 0000h at reset.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
SCLKDIV RES DE1-DE0
Reserved (bits 15-6) – Reserved Bits.
SCLKDIV (bits 5-4) – SCLK Divide. These bits set the SCLK frequency. SCLK is the result of
dividing the internal processor clock by 2, 4, 8, or 16 as in the following table.
SCLKDIV
00b
01b
10b
11b
SCLK Frequency Divider
Processor Clock /2
Processor Clock /4
Processor Clock /8
Processor Clock /16
RES (bits 3-2) – Reserved Bits.
DE1 (bit1) - SDEN1. The SDEN1 bit is held high when this bit is set to 1 and SDEN1 is held low
when this bit is set to 0.
DE0 (bit0) – SDEN0. The SDEN0 bit is held high when this bit is set to 1 and SDEN0 is held low
when this bit is set to 0.
SSS (010h) – Synchronous Serial Status Register.
This is a read only register that indicates the state of the SSI port.
The value of the SSR register is 0000h at reset.
15 14 13 12 11 10 9 8 7 6 5 4 3 2
10
Reserved
RE/TE DR/DT PB
Reserved (bits 15-3) – Reserved Bits.
RE/TE (bit 2) – Receive/Transmit Error Detect. This bit is set to 1 when a read of the Synchronous
Serial Received register or a write to one of the transmit register is detected while the interface is busy
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