IA186EM_04 Datasheet, PDF (48/133 Pages) InnovASIC, Inc – 8/16-Bit Microcontrollers

IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
(PB = 1). This bit is reset to 0 when the SDEN output is not active (DE1-DE0 in the SSC register are
00h).
DR/DT (bit 1) – Data Receive/Transmit Complete. This bit is set to a 1 when the transmission of data
bit 7 is completed (SCLK rising edge) during a transmit or receive operation. This bit is reset by a
read of the SSR register, when either the SSD0 or SSD1 register is written, when the SSS register is
read (unless the SSI completes an operation and sets the bit in the same cycle), or when both SDEN0
and SDEN1 become inactive.
PB (bit 0) SSI Port busy. This bit indicates that a data transmit or receive is occurring when it is set
to 1. When set to 0 it indicates that the port is ready to transmit or receive data.
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