IA186EM_04 Datasheet, PDF (9/133 Pages) InnovASIC, Inc – 8/16-Bit Microcontrollers

IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
RELREG (0feh) - The Peripheral Control Block RELocation REGister maps the entire Peripheral
Control Block Register Bank to either I/O or memory space. In addition, RELREG contains a bit which
places the Interrupt Controller in either Master or Slave mode.
The RELREG contains 20ffh at reset.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RES S/Mn RES IO/Mn
RA [19:8]
RES (bit 15) - Reserved.
S/Mn (bit 14) – A 1 in this bit places the Interrupt Controller into slave mode. When set to zero, the
Interrupt Controller is in master mode.
RES (bit 13) - Reserved.
IO/Mn (bit 12)- A 1 in this bit maps the Peripheral Control Block Register Bank into IO space. When
set to zero, the Peripheral Control Block is mapped into memory space.
RA [19:8] (bits 11-0) – Sets the base address (upper 12 bits) of the Peripheral Control Block Register
Bank. RA [7:0} default to zero. Note that when bit 12 (IO/M_n) is a 1, RA [19:16] are ignored.
RESCON (0f6h) - The RESet CONfiguration Register latches user-defined information present at
specified pins at the rising edge of reset. This contents of this register are read-only and remain valid until
the next reset.
The RESCON contains user-defined information at reset.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RC [15:0]
RC [15:0] (bits 15-0) – At the rising edge of reset, the values of specified pins (ad [15:0] for the
IA186Es and {ao [15:8], ad [7:0]} for the IA188EM) are latched into this register.
PRL (0f4h) - The Processor Release Level Register contains a code corresponding to the latest processor
production release. The PRL is a Read-Only Register
The PRL contains 0400h.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PRL [7:0]
RES
PRL [7:0] (bits 15-8) – The latest Processor Release Level.
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