IA186EM_04 Datasheet, PDF (129/133 Pages) InnovASIC, Inc – 8/16-Bit Microcontrollers

IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
Errata
Version -01
1) Problem: MCS chip select signals (MCS0-3) are intermittently suppressed. All other signals in bus cycle
appear correct (i.e. address, data, write/read strobes).
Analysis: Anomaly occurs when an access to I/O space is immediately followed by an MCS access. Given the
way instruction prefetches naturally separate such accesses, one known scenario for this anomaly is via a DMA
sequence. Possible combinations are:
(1) DMA write to destination is followed by previously scheduled
MCS read or write, (2) DMA from I/O space to MCS space.
Customers using the UART DMA feature of the ES products may be particularly sensitive to this,
because when the TX data register of the PCB is in I/O space, eventually an MCS access will be
corrupted.
Another known scenario occurs when auxiliary flash (containing executable code) is selected by an
MCS signal and the PCB or PCS selects are in I/O space.
The PCB register block and the PCS address spaces are the only areas that can be assigned to I/O
space. The PCB register block is configured by bit 12 of the RELREG, and defaults to I/O space.
PCS space is configured by bit 6 of the MPCS, and must be initialized by the user.
Workaround: If possible, assign PCB and PCS address locations to memory space instead of I/O space.
2) Problem: IA186ES devices do not work in a 188ES socket.
Analysis: The WHB pin should be sampled at reset to configure the bus width. This pin is always
grounded in 188 applications, and floats high during reset in 186 applications. The bus width of the
Innovasic devices are configured via in-package bonding.
Workaround: Use IA188ES devices for 188 sockets.
3) Problem: Noise on TMROUT0 (PIO10) and TMROUT1 (PIO1) when in PIO output mode.
Analysis: Only occurs when application is using HOLD/HLDA function, and either TMROUT pin is
in PIO output mode. Improper logic allows the TMROUT pin to tri-state when HLDA is asserted.
Analysis shows that UZI (PIO26), S6CLK2 (PIO29), DEN (PIO5), and DT_R (PIO4) may also be
affected. PIO input modes and normal operation modes are not affected.
Workaround: If possible, use a PIO pin other than those listed above when utilizing HOLD/HLDA feature. An
external pullup/pulldown may also help.
4) Problem: An extra DMA cycle occurs after ending DMA transfers via a DMA control register write. In certain
applications, this extra DMA cycle occurrence will hang the device because of DREQ/SRDY dependency.
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel [phone] • Fax [phone] • www.Innovasic.com