IA186EM_04 Datasheet, PDF (131/133 Pages) InnovASIC, Inc – 8/16-Bit Microcontrollers

IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
Workaround: To load the CS register use a far JMP command.
10) Problem: There is a difference in how priority of timer interrupts are asserted between the original AMD part
and the Innovasic part.
Analysis: In the original AMD part, timer interrupts cannot be interrupted by another timer interrupt,
even if the new timer interrupt is of a higher priority. The Innovasic part will interrupt a timer
interrupt with a higher priority timer interrupt. Additionally, if a lower priority timer interrupt is
interrupted with a higher priority timer interrupt and another occurrence of the lower priority interrupt
occurs during the processing of the higher priority interrupt, upon execution of the EOI a new lower
priority interrupt will be initiated, possibly orphaning the original lower priority timer interrupt.
Workaround: When using nested interrupts, at the beginning of the interrupt routine before the global
interrupts are enabled with a CLI, timer interrupts must be specifically masked. At the end of the timer
interrupt routine being serviced, you need to set the Interrupt Enable Bit in the Process Status Word to globally
disable interrupts prior to clearing the timer interrupt being serviced.
11) Problem: UART will not respond to break condition if RXD is low when receiver is enabled.
Analysis: Detection of a break only occurs with a falling edge of RXD while receiver is enabled.
Workaround: None.
12) Problem: UART transmitter will not start if TX interrupt conditions exist prior to enabling transmitter.
Analysis: Priority of logic design inadvertently causes this lock up condition .
Workaround: Need to have transmitter enabled prior to any expected data transfers, or clear any spurious
interrupts before enabling .
13) Problem: Lock up just after reset is released.
Analysis: Usually, the first instruction is a long jump to the start of the user's code. In this case, the
compiler apparently inserted a short jump instruction with zero displacement before the expected long
jump instruction. The OEM device stuttered, but recovered to execute the long jump, while the IA
device instruction pointer was corrupted, causing the lock up. In summary, a short jump with zero
displacement is a corner case that does not work in the IA device.
Workaround: Do not use a short jump instruction with zero displacement.
14) Problem: Intermittent startup.
Analysis: Processor either came out of reset normally, or would go into a series of watchdog
timeouts. The addition of 10K ohm pullups to the WR_n and RD_n outputs seemed to solve the issue.
Further analysis of the OEM device shows the presence of undocumented pullups on these pins,
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