IA186EM_04 Datasheet, PDF (56/133 Pages) InnovASIC, Inc – 8/16-Bit Microcontrollers

IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
Direct Memory Access (DMA)
Direct memory access (DMA) relieves the CPU of involvement in the transfer of data between memory
and peripherals over either one or both high-speed DMA channels. Data can be transferred from memory
to I/O, I/O to memory, memory-to-memory, or I/O-to-I/O. Furthermore, the DMA channels can be
connected to the asynchronous serial port.
The IA186EM microcontroller supports the transfer of both bytes and words, to and from, even or odd
addresses, but it does not support word transfers to memory that is configured for byte accesses. The
IA188EM does not support word transfers at all. Each data transfer will take two bus cycles (a minimum
of 8 clock cycles).
There are three sources of DMA requests for each DMA channel: the channel request pin (drq1 – drq0),
Timer2, or the system software. The two channels can be programmed to have different priorities to
facilitate the resolution of simultaneous DMA requests or to interrupt a transfer on the other channel.
DMA Operation
The Peripheral Control Block contains six registers for each DMA channel to control and specify the
operation of the channels. The six registers consist of a pair of registers to store a 20-bit source address, a
pair of registers to store a 20-bit destination address, a 16-bit transfer count register, and a 16-bit control
register.
The number of DMA transfers required is designated in the DMA Transfer Count register and can be up
to 64K bytes or words and, furthermore, will end automatically. DMA channel function is defined by the
Control registers, which along with the other 5 registers can be changed at any time, including during a
DMA transfer and are implemented immediately.
DMA Channel Control Registers
See D1CON (0dah) & D0CON (0cah) - DMA CONtrol Registers above. Briefly, these registers specify
the following:
" Is the data destination in memory or I/O space? (Bit 15).
" Is the destination address incremented, decremented, or unchanged after each transfer? (Bit 14 & 13).
" Is the data source in memory or I/O space? (Bit 12).
" Is the source address incremented, decremented, or unchanged after each transfer? (Bit 11 & 10).
" Do DMA transfers cease upon reaching a designated count? (Bit 9).
" Does the last transfer generate an interrupt? (Bit 8).
" Synchronization mode. (Bits 7 & 6).
" The relative priority of one DMA channel with respect to the other. (Bit 5).
" Acceptance of DMA requests from Timer2. (Bit 4).
" Byte or word transfers. (Bit 0).
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