MC68HC08GP32A Datasheet, PDF (99/258 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10
Low-Voltage Inhibit (LVI)
10.1 Introduction
This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the V_DD pin
and can force a reset when the V_DD voltage falls below the LVI trip falling voltage, V_TRIPF.
10.2 Features
Features of the LVI module include:
• Programmable LVI reset
• Selectable LVI trip voltage
• Programmable stop mode operation
10.3 Functional Description
Figure 10-1 shows the structure of the LVI module. The LVI module contains a bandgap reference circuit
and comparator. Clearing the LVI power disable bit, LVIPWRD, enables the LVI to monitor V_DD voltage.
Clearing the LVI reset disable bit, LVIRSTD, enables the LVI module to generate a reset when V_DD falls
below a voltage, V_TRIPF. Setting the LVI enable in stop mode bit, LVISTOP, enables the LVI to operate in
stop mode. Setting the LVI 5-V or 3-V trip point bit, LVI5OR3, enables the trip point voltage, V_TRIPF, to be
configured for 5-V operation. Clearing the LVI5OR3 bit enables the trip point voltage, V_TRIPF, to be
configured for 3-V operation. The actual trip points are shown in Chapter 20 Electrical Specifications.
LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the mask option register. See 11.2 Mask Option
Registers for details of the LVI’s configuration bits. Once an LVI reset occurs, the MCU remains in reset
until V_DD rises above a voltage, V_TRIPR, which causes the MCU to exit reset. See 15.3.2.5 Low-Voltage
Inhibit (LVI) Reset for details of the interaction between the SIM and the LVI. The output of the comparator
controls the state of the LVIOUT flag in the LVI status register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.
10.3.1 Polled LVI Operation
In applications that can operate at V_DD levels below the V_TRIPF level, software can monitor V_DD by polling
the LVIOUT bit. In the mask option register, the LVIPWRD bit must be 0 to enable the LVI module, and
the LVIRSTD bit must be 1 to disable LVI resets.
10.3.2 Forced Reset Operation
In applications that require V_DD to remain above the V_TRIPF level, enabling LVI resets allows the LVI
module to reset the MCU when V_DD falls below the V_TRIPF level. In the mask option register, the
LVIPWRD and LVIRSTD bits must be 0 to enable the LVI module and to enable LVI resets.
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor
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