MC68HC08GP32A Datasheet, PDF (128/258 Pages) Freescale Semiconductor, Inc – Microcontrollers

Resets and Interrupts
CLI
LDA #$FF
INT1
PSHH
PULH
RTI
BACKGROUND
ROUTINE
INT1 INTERRUPT SERVICE ROUTINE
INT2
PSHH
PULH
RTI
INT2 INTERRUPT SERVICE ROUTINE
Figure 13-5. Interrupt Recognition Example
The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the
INT1 RTI prefetch, this is a redundant operation.
NOTE
To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, save the H
register and then restore it prior to exiting the routine.
13.3.2 Sources
The sources in Table 13-1 can generate CPU interrupt requests.
13.3.2.1 SWI Instruction
The software interrupt instruction (SWI) causes a non-maskable interrupt.
NOTE
A software interrupt pushes PC onto the stack. An SWI does not push PC
– 1, as a hardware interrupt does.
13.3.2.2 Break Interrupt
The break module causes the CPU to execute an SWI instruction at a software-programmable break
point.
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
128
Freescale Semiconductor