MC68HC08GP32A Datasheet, PDF (157/258 Pages) Freescale Semiconductor, Inc – Microcontrollers

NORMAL FLAG CLEARING SEQUENCE
I/O Registers
BYTE 1
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 1
BYTE 2
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 2
BYTE 3
DELAYED FLAG CLEARING SEQUENCE
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 3
BYTE 4
BYTE 1
BYTE 2
BYTE 3
READ SCS1
SCRF = 1
OR = 0
READ SCS1
SCRF = 1
OR = 1
READ SCDR
BYTE 1
READ SCDR
BYTE 3
Figure 14-14. Flag Clearing Sequence
BYTE 4
14.8.5 SCI Status Register 2
SCI status register 2 contains flags to signal the following conditions:
• Break character detected
• Incoming data
Address: $0017
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BKF
RPF
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-15. SCI Status Register 2 (SCS2)
BKF — Break Flag Bit
This clearable, read-only bit is set when the SCI detects a break character on the PTE1/RxD pin. In
SCS1, the FE and SCRF bits are also set. In 9-bit character transmissions, the R8 bit in SCC3 is
cleared. BKF does not generate a CPU interrupt request. Clear BKF by reading SCS2 with BKF set
and then reading the SCDR. Once cleared, BKF can become set again only after 1s again appear on
the PTE1/RxD pin followed by another break character. Reset clears the BKF bit.
1 = Break character detected
0 = No break character detected
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor
157