MC68HC08GP32A Datasheet, PDF (225/258 Pages) Freescale Semiconductor, Inc – Microcontrollers

Monitor Module (MON)
MC68HC08GP32A/MC68HC08GP16A _VDD
NC _RST
1 µF
1 µF
DB9
2
3
MAX232
V_DD
1 _C1+
+
3 _C1–
V_CC ¹⁶
GND ¹⁵
+
1 µF
1 µF
+
4 _C2+
+
5 _C2–
7
8
V+ ²
V– ⁶
10
9
1 µF
+
74HC125
6
5
74HC125
2
3
4
9.8304 MHz
1 kΩ
V_DD
9.1 V
10 kΩ
OSC1
IRQ
PTA0
5
1
V_DD
V_DDA
0.1 µF
V_DD
10 k
PTC3
10 k
PTC0
10 k
PTC1
10 k
PTA7
V_SSA
V_SS
Figure 19-9. Normal Monitor Mode Circuit
19.3.1.1 Monitor Mode Entry
Table 19-2 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
may be entered after a power-on reset (POR) and will allow communication provided the pin and clock
conditions are met.
The rising edge of the internal RST signal latches the monitor mode. Once monitor mode is latched, the
values on PTA7, PTC0, PTC1, and PTC3 pins can be changed.
Once out of reset, the MCU waits for the host to send eight security bytes (see 19.3.2 Security). After the
security bytes, the MCU sends a break signal (10 consecutive 0s) to the host, indicating that it is ready to
receive a command.
19.3.1.2 Monitor Vectors
In monitor mode, the MCU uses different vectors for reset, SWI (software interrupt), and break interrupt
than those for user mode. The alternate vectors are in the $FE page instead of the $FF page and allow
code execution from the internal monitor firmware instead of user code. The COP module is disabled in
monitor mode as long as V_TST is applied to either the IRQ pin or the RST pin.
Table 19-1 summarizes the differences between user mode and monitor mode regarding vectors.
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor
225