MC68HC08GP32A Datasheet, PDF (238/258 Pages) Freescale Semiconductor, Inc – Microcontrollers

Electrical Specifications
20.8 3.0-V Control Timing
Characteristic⁽¹⁾
Symbol
Min
Max
Unit
Frequency of operation⁽²⁾
Crystal option
External clock option⁽³⁾
f_OSC
32
dc⁽⁴⁾
100
kHz
16.4
MHz
Internal operating frequency
Internal clock period (1/f_OP)
RST input pulse width low⁽⁵⁾
IRQ interrupt pulse width low⁽⁶⁾ (edge-triggered)
IRQ interrupt pulse period
f_OP (f_BUS)
t_CYC
t_IRL
t_ILIH
t_ILIL
—
244
125
125
Note⁽⁷⁾
4.1
MHz
—
ns
—
ns
—
ns
—
t_CYC
1. V_SS = 0 Vdc; timing shown with respect to 20% V_DD and 70% V_DD unless otherwise noted.
2. See 20.16 Clock Generation Module Characteristics for more information.
3. No more than 10% duty cycle deviation from 50%
4. Some modules may require a minimum frequency greater than dc for proper operation. See appropriate table for this in-
formation.
5. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
6. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to be recognized.
7. The minimum period, t_ILIL, should not be less than the number of cycles it takes to execute the interrupt service routine
plus t_CYC.
t_RL
RST
t_ILIL
t_ILIH
IRQ
Figure 20-1. RST and IRQ Timing
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
238
Freescale Semiconductor