MC68HC08GP32A Datasheet, PDF (163/258 Pages) Freescale Semiconductor, Inc – Microcontrollers

SIM Bus Clock Control and Generation
Addr.
Register Name
Bit 7
6
5
4
3
2
Interrupt Status Register 1 ^{Read: IF6}
IF5
IF4
IF3
IF2
IF1
$FE04
(INT1) Write: R
R
R
R
R
R
See page 171. _Reset:
0
0
0
0
0
0
Interrupt Status Register 2 ^{Read: IF14}
IF13
IF12
IF11
IF10
IF9
$FE05
(INT2) Write: R
R
R
R
R
R
See page 172. _Reset:
0
0
0
0
0
0
Interrupt Status Register 3 ^Read:
0
0
0
0
0
0
$FE06
(INT3) Write: R
R
R
R
R
R
See page 172. _Reset:
0
0
0
0
0
0
= Unimplemented
Figure 15-2. SIM I/O Register Summary (Continued)
1
Bit 0
0
0
R
R
0
0
IF8
IF7
R
R
0
0
IF16
IF15
R
R
0
0
15.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 15-3. This clock can
come from either an external oscillator or from the on-chip PLL. (See Chapter 4 Clock Generator Module
(CGM).)
OSC2
OSC1
OSCILLATOR (OSC)
CGMXCLK
TO TIMTB15A, ADC
OSCSTOPENB
FROM
MOR
CGMRCLK
PHASE-LOCKED LOOP (PLL)
CGMOUT
SIM
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
SIMOSCEN
IT12
TO REST
OF CHIP
IT23
TO REST
OF CHIP
SIMDIV2
MONITOR MODE
USER MODE
PTC3
Figure 15-3. CGM Clock Signals
15.2.1 Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator output (CGMXCLK) divided by four
or the PLL output (CGMVCLK) divided by four.
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor
163