MC68HC08GP32A Datasheet, PDF (172/258 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
Interrupt Status Register 2
Address: $FE05
Bit 7
6
5
4
3
2
Read: IF14
IF13
IF12
IF11
IF10
IF9
Write: R
R
R
R
R
R
Reset: 0
0
0
0
0
0
R
= Reserved
1
Bit 0
IF8
IF7
R
R
0
0
Figure 15-13. Interrupt Status Register 2 (INT2)
IF14–IF7 — Interrupt Flags 14–7
These flags indicate the presence of interrupt requests from the sources shown in Table 15-3.
1 = Interrupt request present
0 = No interrupt request present
Interrupt Status Register 3
Address: $FE06
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
0
0
IF16
IF15
Write: R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
R
= Reserved
Figure 15-14. Interrupt Status Register 3 (INT3)
Bits 7–2 — Always read 0
IF16–IF15 — Interrupt Flags 16–15
These flags indicate the presence of an interrupt request from the source shown in Table 15-3.
1 = Interrupt request present
0 = No interrupt request present
15.5.2 Reset
All reset sources always have equal and highest priority and cannot be arbitrated.
15.5.3 Break Interrupts
The break module can stop normal program flow at a software-programmable break point by asserting its
break interrupt output. (See Chapter 18 Timer Interface Modules (TIM1 and TIM2).) The SIM puts the
CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection
of each module to see how each module is affected by the break state.
15.5.4 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can be cleared during break mode. The
user can select whether flags are protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the SIM break flag control register (SBFCR).
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
172
Freescale Semiconductor