MC68HC08GP32A Datasheet, PDF (144/258 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Communications Interface (SCI) Module
PTE1/RxD
START BIT
LSB
SAMPLES
START BIT
QUALIFICATION
START BIT
VERIFICATION
DATA
SAMPLING
RT
CLOCK
RT CLOCK
STATE
RT CLOCK
RESET
Figure 14-7. Receiver Data Sampling
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7.
Table 14-2 summarizes the results of the start bit verification samples.
Table 14-2. Start Bit Verification
RT3, RT5, and RT7
Samples
000
001
010
011
100
101
110
111
Start Bit
Verification
Yes
Yes
Yes
No
Yes
No
No
No
Noise Flag
0
1
1
0
1
0
0
0
Start bit verification is not successful if any two of the three verification samples are 1s. If start bit
verification is not successful, the RT clock is reset and a new search for a start bit begins.
To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and
RT10. Table 14-3 summarizes the results of the data bit samples.
Table 14-3. Data Bit Recovery
RT8, RT9, and RT10
Samples
000
001
010
011
Data Bit
Determination
0
0
0
1
Noise Flag
0
1
1
1
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
144
Freescale Semiconductor