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MC68HC08GP32A Datasheet, PDF (235/258 Pages) Freescale Semiconductor, Inc – Microcontrollers
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5.0-V DC Electrical Characteristics
Characteristic(1)
Input high voltage
All ports, IRQ, RST, OSC1
Symbol
VIH
Min
0.7 × VDD
Typ(2)
—
Max
VDD
Unit
V
Input low voltage
All ports, IRQ, RST, OSC1
VIL
VSS
—
0.2 × VDD
V
VDD supply current
Run(3)
Wait(4)
Stop(5)
25°C
25°C with TBM enabled(6)
25°C with LVI and TBM enabled(6)
–40°C to 85°C
–40°C to 85°C with TBM enabled(6)
–40°C to 85°C with LVI and TBM enabled(6)
—
15
20
mA
—
4
8
mA
IDD
—
2
—
µA
—
20
—
µA
—
300
—
µA
—
—
35
µA
—
50
—
µA
—
500
—
µA
I/O ports Hi-Z leakage current(7)
Input current
Pullup resistors (as input only)
Ports PTA7/KBD7–PTA0/KBD0, PTC6–PTC0,
PTD7/T2CH1–PTD0/SS
IIL
–10
—
+10
µA
IIn
–1
—
+1
µA
RPU
20
45
65
kΩ
Capacitance
Ports (as input or output)
Monitor mode entry voltage
Low-voltage inhibit, trip falling voltage
Low-voltage inhibit, trip rising voltage
Low-voltage inhibit reset/recover hysteresis
(VTRIPF + VHYS = VTRIPR)
POR rearm voltage(8)
POR reset voltage(9)
POR rise time ramp rate(10)
COut
CIn
VTST
VTRIPF
VTRIPR
VHYS
VPOR
VPORRST
RPOR
—
—
VDD + 2.5
3.90
4.00
—
0
0
0.035
—
—
—
4.25
4.35
100
—
700
—
12
8
pF
9.1
V
4.50
V
4.60
V
—
mV
100
mV
800
mV
—
V/ms
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Run (operating) IDD measured using external square wave clock source (fOSC = 32.8 MHz). All inputs 0.2 V from rail. No
dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fOSC = 32.8 MHz). All inputs 0.2 V from rail. No dc loads.
Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects
wait IDD. Measured with PLL and LVI enabled.
5. Stop IDD is measured with OSC1 = VSS.
6. Stop IDD with TBM enabled is measured using an external square wave clock source (fOSC = 32.8 MHz). All inputs 0.2V
from rail. No dc loads. Less than 100 pF on all outputs. All inputs configured as inputs.
7. Pullups and pulldowns are disabled. Port B leakage is specified in 20.12 ADC Characteristics.
8. Maximum is highest voltage that POR is guaranteed.
9. Maximum is highest voltage that POR is possible.
10. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VDD is reached.
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor
235
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