MC68HC08GP32A Datasheet, PDF (111/258 Pages) Freescale Semiconductor, Inc – Microcontrollers

Figure 12-4 shows the port A I/O logic.
READ DDRA ($0004)
WRITE DDRA ($0004)
RESET
WRITE PTA ($0000)
DDRAx
PTAx
PTAPUEx
Port A
V_DD
INTERNAL
PULLUP
DEVICE
PTAx
READ PTA ($0000)
Figure 12-4. Port A I/O Circuit
When bit DDRAx is a 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a 0,
reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-2 summarizes the operation of the port A pins.
Table 12-2. Port A Pin Functions
PTAPUE Bit DDRA Bit PTA Bit I/O Pin Mode
1
0
X⁽¹⁾
Input, V_DD(4)
0
0
X
Input, Hi-Z⁽²⁾
X
1
X
Output
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
4. I/O pin pulled up to V_DD by internal pullup device
Accesses to DDRA
Read/Write
DDRA7–DDRA0
DDRA7–DDRA0
DDRA7–DDRA0
Accesses to PTA
Read
Write
Pin
PTA7–PTA0⁽³⁾
Pin
PTA7–PTA0⁽³⁾
PTA7–PTA0
PTA7–PTA0
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor
111