MC68HC08GP32A Datasheet, PDF (167/258 Pages) Freescale Semiconductor, Inc – Microcontrollers

SIM Counter
15.3.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP
bit in the SIM reset status register (SRSR) and causes a reset.
If the stop enable bit, STOP, in the mask option register is 0, the SIM treats the STOP instruction as an
illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal
reset sources.
15.3.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the
CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively
pulls down the RST pin for all internal reset sources.
15.3.2.5 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit module (LVI) asserts its output to the SIM when the V_DD voltage falls to the V_TRIPF
voltage. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin (RST) is held
low if the LVIPWRD and LVIRSTD bits in the mask option register are 0. The RST pin will be held low
while the SIM counter counts out 4096 + 32 CGMXCLK cycles after V_DD rises above V_TRIPR. Thirty-two
CGMXCLK cycles later, the CPU is released from reset to allow the reset vector sequence to occur. The
SIM actively pulls down the RST pin for all internal reset sources.
15.4 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the
oscillator time to stabilize before enabling the internal bus clocks. The SIM counter also serves as a
prescaler for the computer operating properly module (COP). The SIM counter overflow supplies the clock
for the COP module. The SIM counter is 12 bits long.
15.4.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit
asserts the signal PORRST. Once the SIM is initialized, it enables the clock generation module (CGM) to
drive the bus clock state machine.
15.4.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After
an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the mask
option register. If the SSREC bit is a 1, then the stop recovery is reduced from the normal delay of 4096
CGMXCLK cycles down to 32 CGMXCLK cycles. This is ideal for applications using crystals with the
OSCSTOPENB bit set. External crystal applications should use the full stop recovery time, SSREC
cleared, with the OSCSTOPENB bit cleared.
15.4.3 SIM Counter and Reset States
External reset has no effect on the SIM counter. (See 15.6.2 Stop Mode for details.) The SIM counter is
free-running after all reset states. (See 15.3.2 Active Resets from Internal Sources for counter control and
internal reset recovery sequences.)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor
167