MC68HC08GP32A Datasheet, PDF (168/258 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
15.5 Exception Control
Normal, sequential program execution can be changed in three different ways:
• Interrupts:
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
• Reset
• Break interrupts
15.5.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers
the CPU register contents from the stack so that normal processing can resume. Figure 15-8 shows
interrupt entry timing. Figure 15-9 shows interrupt recovery timing.
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared). (See Figure 15-10.)
MODULE
INTERRUPT
I BIT
IAB
IDB
R/W
MODULE
INTERRUPT
I BIT
IAB
IDB
R/W
DUMMY
SP
SP – 1 SP – 2 SP – 3 SP – 4 VECT H VECT L START ADDR
DUMMY PC – 1[7:0] PC – 1[15:8] X
A
CCR V DATA H V DATA L OPCODE
Figure 15-8. Interrupt Entry Timing
SP – 4 SP – 3 SP – 2 SP – 1
SP
PC
PC + 1
CCR
A
X PC – 1 [15:8] PC – 1 [7:0] OPCODE OPERAND
Figure 15-9. Interrupt Recovery Timing
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
168
Freescale Semiconductor