MC68HC08GP32A Datasheet, PDF (162/258 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
STOP/WAIT
CONTROL
SIM
COUNTER
÷2
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO CGM)
COP CLOCK
CGMXCLK (FROM CGM)
CGMOUT (FROM CGM)
RESET
PIN LOGIC
V_DD
INTERNAL
PULLUP
DEVICE
CLOCK
CONTROL
CLOCK GENERATORS
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
MASTER
RESET
CONTROL
RESET
INTERNAL CLOCKS
LVI (FROM LVI MODULE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
INTERRUPT CONTROL
AND PRIORITY DECODE
Figure 15-1. SIM Block Diagram
INTERRUPT SOURCES
CPU INTERFACE
Addr.
Register Name
Bit 7
6
5
4
3
SIM Break Status Register ^Read:
R
R
R
R
R
$FE00
(SBSR) Write:
See page 175. _Reset:
Note: Writing a 0 clears SBSW.
SIM Reset Status Register ^{Read: POR}
PIN
COP
ILOP
ILAD
$FE01
(SRSR) Write:
See page 176. _POR:
1
0
0
0
0
$FE02
Reserved
R
R
R
R
R
2
1
Bit 0
SBSW
R
R
Note
0
0
LVI
0
0
0
0
R
R
R
SIM Break Flag Control ^Read: _BCFE
R
R
R
R
R
R
R
$FE03
Register (SBFCR) Write:
See page 177. _Reset:
0
Figure 15-2. SIM I/O Register Summary
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
162
Freescale Semiconductor