MC68HC08GP32A Datasheet, PDF (100/258 Pages) Freescale Semiconductor, Inc – Microcontrollers

Low-Voltage Inhibit (LVI)
V_DD
LVIPWRD
FROM MOR
STOP INSTRUCTION
FROM MOR
LVIRSTD
LVISTOP
FROM MOR
LOW V_DD
DETECTOR
V_DD > LVI_Trip = 0
V_DD ≤ LVI_Trip = 1
LVI5OR3
FROM MOR
LVIOUT
Figure 10-1. LVI Module Block Diagram
LVI RESET
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
0
0
0
0
0
0
0
LVI Status Register
$FE0C
(LVISR) Write:
See page 101.
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 10-2. LVI I/O Register Summary
10.3.3 Voltage Hysteresis Protection
Once the LVI has triggered (by having V_DD fall below V_TRIPF), the LVI will maintain a reset condition until
V_DD rises above the rising trip point voltage, V_TRIPR. This prevents a condition in which the MCU is
continually entering and exiting reset if V_DD is approximately equal to V_TRIPF. V_TRIPR is greater than
V_TRIPF by the hysteresis voltage, V_HYS.
10.3.4 LVI Trip Selection
The LVI5OR3 bit in the mask option register selects whether the LVI is configured for 5-V or 3-V
protection.
NOTE
The microcontroller is guaranteed to operate at a minimum supply voltage.
The trip point (V_TRIPF [5 V] or V_TRIPF [3 V]) may be lower than this. (See
Chapter 20 Electrical Specifications for the actual trip point voltages.)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
100
Freescale Semiconductor