MC68HC08GP32A Datasheet, PDF (215/258 Pages) Freescale Semiconductor, Inc – Microcontrollers

I/O Registers
Address: T1MODH, $0023 and T2MODH, $002E
Bit 7
6
5
4
3
2
Read:
Bit 15
14
13
12
11
10
Write:
Reset: 1
1
1
1
1
1
1
Bit 0
9
Bit 8
1
1
Figure 18-8. TIM Counter Modulo Register High (TMODH)
Address: T1MODL, $0024 and T2MODL, $002F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset: 1
1
1
1
1
1
1
1
Figure 18-9. TIM Counter Modulo Register Low (TMODL)
NOTE
Reset the TIM counter before writing to the TIM counter modulo registers.
18.9.4 TIM Channel Status and Control Registers
Each of the TIM channel status and control registers:
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input capture trigger
• Selects output toggling on TIM overflow
• Selects 0% and 100% PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
Address: T1SC0, $0025 and T2SC0, $0030
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
CH0F
0
CH0IE
MS0B
MS0A
ELS0B ELS0A
TOV0 CH0MAX
Reset: 0
0
0
0
0
0
0
0
Figure 18-10. TIM Channel 0 Status and Control Register (TSC0)
Address: T1SC1, $0028 and T2SC1, $0033
Bit 7
6
5
4
3
2
1
Bit 0
Read: CH1F
0
CH1IE
MS1A ELS1B ELS1A TOV1 CH1MAX
Write: 0
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 18-11. TIM Channel 1 Status and Control Register (TSC1)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor
215