MC68HC08GP32A Datasheet, PDF (214/258 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Modules (TIM1 and TIM2)
Table 18-2. Prescaler Selection
PS2
PS1
PS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
TIM Clock Source
Internal bus clock ÷ 1
Internal bus clock ÷ 2
Internal bus clock ÷ 4
Internal bus clock ÷ 8
Internal bus clock ÷ 16
Internal bus clock ÷ 32
Internal bus clock ÷ 64
Not available
18.9.2 TIM Counter Registers
The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter.
Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent
reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter
registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.
NOTE
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by reading TCNTL before exiting
the break interrupt. Otherwise, TCNTL retains the value latched during the break.
Address: T1CNTH, $0021 and T2CNTH, $002C
Bit 7
6
5
4
3
2
Read: Bit 15
14
13
12
11
10
Write:
Reset: 0
0
0
0
0
0
= Unimplemented
1
Bit 0
9
Bit 8
0
0
Figure 18-6. TIM Counter Registers High (TCNTH)
Address: T1CNTL, $0022 and T2CNTL, $002D
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 18-7. TIM Counter Registers Low (TCNTL)
18.9.3 TIM Counter Modulo Registers
The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter
reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting
from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow
interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
214
Freescale Semiconductor