MC68HC08GP32A Datasheet, PDF (33/258 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output (I/O) Section
Addr.
Register Name
Timer 2 Channel 0 Status and ^Read:
$0030 Control Register (T2SC0) Write:
See page 215. _Reset:
$0031
Timer 2 Channel 0 ^Read:
Register High (T2CH0H) Write:
See page 218. _Reset:
$0032
Timer 2 Channel 0 ^Read:
Register Low (T2CH0L) Write:
See page 218. _Reset:
Timer 2 Channel 1 Status and ^Read:
$0033 Control Register (T2SC1) Write:
See page 215. _Reset:
$0034
Timer 2 Channel 1 ^Read:
Register High (T2CH1H) Write:
See page 218. _Reset:
$0035
Timer 2 Channel 1 ^Read:
Register Low (T2CH1L) Write:
See page 218. _Reset:
$0036
PLL Control Register ^Read:
(PCTL) Write:
See page 59. _Reset:
$0037
PLL Bandwidth Control ^Read:
Register (PBWC) Write:
See page 61. _Reset:
$0038
PLL Multiplier Select High ^Read:
Register (PMSH) Write:
See page 61. _Reset:
$0039
PLL Multiplier Select Low ^Read:
Register (PMSL) Write:
See page 62. _Reset:
$003A
PLL VCO Range Select ^Read:
Register (PMRS) Write:
See page 62. _Reset:
$003B
PLL Reference Divider ^Read:
Select Register (PMDS) Write:
See page 63. _Reset:
Bit 7
CH0F
0
0
Bit 15
Bit 7
CH1F
0
0
Bit 15
Bit 7
PLLIE
0
AUTO
0
0
0
MUL7
0
VRS7
0
0
0
6
5
4
3
2
1
CH0IE MS0B MS0A ELS0B ELS0A TOV0
0
0
0
0
0
0
14
13
12
11
10
9
Indeterminate after reset
6
5
4
3
2
1
CH1IE
Indeterminate after reset
0
MS1A ELS1B ELS1A TOV1
0
0
0
0
0
0
14
13
12
11
10
9
Indeterminate after reset
6
5
4
3
2
1
Indeterminate after reset
PLLF
PLLON
BCS
PRE1
PRE0
VPR1
0
1
0
0
0
0
LOCK
0
0
0
0
ACQ
0
0
0
0
0
0
0
0
0
MUL11 MUL10 MUL9
0
0
0
0
0
0
MUL6
MUL5
MUL4
MUL3
MUL2
MUL1
1
0
0
0
0
0
VRS6
VRS5
VRS4
VRS3
VRS2
VRS1
1
0
0
0
0
0
0
0
0
RDS3
RDS2
RDS1
0
0
= Unimplemented
0
0
R = Reserved
0
0
U = Unaffected
Bit 0
CH0MAX
0
Bit 8
Bit 0
CH1MAX
0
Bit 8
Bit 0
VPR0
0
R
0
MUL8
0
MUL0
0
VRS0
0
RDS0
1
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 7)
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor
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