MC68HC08GP32A Datasheet, PDF (94/258 Pages) Freescale Semiconductor, Inc – Microcontrollers

Low-Power Modes
9.3 Break Module (BRK)
9.3.1 Wait Mode
If enabled, the break module is active in wait mode. In the break routine, the user can subtract one from
the return address on the stack if the SBSW bit in the break status register is set.
9.3.2 Stop Mode
The break module is inactive in stop mode. The STOP instruction does not affect break module register
states.
9.4 Central Processor Unit (CPU)
9.4.1 Wait Mode
The WAIT instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from
wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
9.4.2 Stop Mode
The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After
exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
9.5 Clock Generator Module (CGM)
9.5.1 Wait Mode
The CGM remains active in wait mode. Before entering wait mode, software can disengage and turn off
the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL). Less power-sensitive
applications can disengage the PLL without turning it off. Applications that require the PLL to wake the
MCU from wait mode also can deselect the PLL output without turning off the PLL.
9.5.2 Stop Mode
If the OSCSTOPENB bit in the MOR register is cleared (default), then the STOP instruction disables the
CGM (oscillator and phase-locked loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and
CGMINT).
If the OSCSTOPENB bit in the MOR register is set, then the phase locked loop is shut off but the oscillator
will continue to operate in stop mode.
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
94
Freescale Semiconductor