MC68HC08GP32A Datasheet, PDF (126/258 Pages) Freescale Semiconductor, Inc – Microcontrollers

Resets and Interrupts
The register is initialized on power-up as shown with the POR bit set and all other bits cleared. During a
POR or any other internal reset, the RST pin is pulled low. After the pin is released, it will be sampled 32
CGMXCLK cycles later. If the pin is not above a V_IH at that time, then the PIN bit in the SRSR may be set
in addition to whatever other bits are set.
NOTE
Only a read of the SIM reset status register clears all reset flags. After
multiple resets from different sources without reading the register, multiple
flags remain set.
Address: $FE01
Bit 7
Read: POR
Write:
POR: 1
6
5
PIN
COP
0
0
= Unimplemented
4
3
2
ILOP
ILAD
0
0
0
0
R
= Reserved
1
Bit 0
LVI
0
0
0
Figure 13-3. SIM Reset Status Register (SRSR)
POR — Power-On Reset Flag
1 = Power-on reset since last read of SRSR
0 = Read of SRSR since last power-on reset
PIN — External Reset Flag
1 = External reset via RST pin since last read of SRSR
0 = POR or read of SRSR since last external reset
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by timeout of COP counter
0 = POR or read of SRSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
ILAD — Illegal Address Reset Bit
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
LVI — Low-Voltage Inhibit Reset Bit
1 = Last reset caused by low-power supply voltage
0 = POR or read of SRSR
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
126
Freescale Semiconductor