MC68HC08GP32A Datasheet, PDF (161/258 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 15
System Integration Module (SIM)
15.1 Introduction
This section describes the system integration module (SIM). Together with the CPU, the SIM controls all
MCU activities. A block diagram of the SIM is shown in Figure 15-1. Table 15-1 is a summary of the SIM
input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception
timing.
The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals:
– Stop/wait/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and COP timeout
• Interrupt arbitration
Table 15-1 shows the internal signal names used in this section.
Table 15-1. Signal Name Conventions
Signal Name
CGMXCLK
CGMVCLK
CGMOUT
IAB
IDB
PORRST
IRST
R/W
Description
Buffered version of OSC1 from clock generator module (CGM)
PLL output
PLL-based or OSC1-based clock output from CGM module
(Bus clock = CGMOUT divided by two)
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor
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