MC68HC08GP32A Datasheet, PDF (226/258 Pages) Freescale Semiconductor, Inc – Microcontrollers

Development Support
Table 19-1. Mode Differences
Modes
User
COP
Enabled
Reset
Vector High
$FFFE
Reset
Vector Low
$FFFF
Functions
Break
Vector High
$FFFC
Break
Vector Low
$FFFD
SWI
Vector High
$FFFC
SWI
Vector Low
$FFFD
Monitor _Disabled⁽¹⁾
$FEFE
$FEFF
$FEFC
$FEFD
$FEFC
$FEFD
1. If the high voltage (V_TST) is removed from the IRQ pin while in monitor mode, the SIM asserts its COP enable output. The
COP is a mask option enabled or disabled by the COPD bit in the mask option register. (See 20.5 5.0-V DC Electrical Char-
acteristics.)
19.3.1.3 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.
Transmit and receive baud rates must be identical.
START
BIT BIT 0
BIT 1 BIT 2 BIT 3 BIT 4 BIT 5
NEXT
START
BIT 6 BIT 7 STOP BIT
BIT
Figure 19-10. Monitor Data Format
19.3.1.4 Break Signal
A start bit (0) followed by nine 0 bits is a break signal. When the monitor receives a break signal, it drives
the PTA0 pin high for the duration of two bits and then echoes back the break signal.
MISSING STOP BIT
2-STOP BIT DELAY BEFORE ZERO ECHO
01234567
01234567
Figure 19-11. Break Transaction
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
226
Freescale Semiconductor