MC68HC08GP32A Datasheet, PDF (237/258 Pages) Freescale Semiconductor, Inc – Microcontrollers

5.0-V Control Timing
Characteristic⁽¹⁾
Symbol
Min
Typ⁽²⁾
Max
Unit
Low-voltage inhibit, trip falling voltage
Low-voltage inhibit, trip rising voltage
Low-voltage inhibit reset/recover hysteresis
(V_TRIPF + V_HYS = V_TRIPR)
POR rearm voltage⁽⁹⁾
POR reset voltage⁽¹⁰⁾
V_TRIPF
2.45
2.60
2.70
V
V_TRIPR
2.50
2.66
2.80
V
V_HYS
—
60
—
mV
V_POR
0
V_PORRST
0
—
100
mV
700
800
mV
POR rise time ramp rate⁽¹¹⁾
R_POR
0.02
—
—
V/ms
1. V_DD = 3.0 Vdc ± 10%, V_SS = 0 Vdc, T_A = T_L to T_H, unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Run (operating) I_DD measured using external square wave clock source (f_OSC = 16.4 MHz). All inputs 0.2V from rail. No
dc loads. Less than 100 pF on all outputs. C_L = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run I_DD. Measured with all modules enabled.
4. Wait I_DD measured using external square wave clock source (f_OSC = 16.4 MHz). All inputs 0.2 V from rail. No dc loads.
Less than 100 pF on all outputs. C_L = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects
wait I_DD. Measured with PLL and LVI enabled.
5. Stop I_DD is measured with OSC1 = V_SS.
6. Stop I_DD with TBM enabled is measured using an external square wave clock source (f_OSC = 16.4 MHz). All inputs 0.2 V
from rail. No dc loads. Less than 100 pF on all outputs. All inputs configured as inputs.
7. Measured with TBM enabled using 32-kHz crystal.
8. Pullups and pulldowns are disabled.
9. Maximum is highest voltage that POR is guaranteed.
10. Maximum is highest voltage that POR is possible.
11. If minimum V_DD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
V_DD is reached.
20.7 5.0-V Control Timing
Characteristic⁽¹⁾
Symbol
Min
Max
Unit
Frequency of operation⁽²⁾
Crystal option
External clock option⁽³⁾
f_OSC
32
dc⁽⁴⁾
100
kHz
32.8
MHz
Internal operating frequency
Internal clock period (1/f_OP)
RST input pulse width low⁽⁵⁾
IRQ interrupt pulse width low⁽⁶⁾ (edge-triggered)
IRQ interrupt pulse period
f_OP (f_BUS)
t_CYC
t_RL
t_ILIH
t_ILIL
—
122
50
50
Note⁽⁷⁾
8.2
MHz
—
ns
—
ns
—
ns
—
t_CYC
1. V_SS = 0 Vdc; timing shown with respect to 20% V_DD and 70% V_DD unless otherwise noted.
2. See 20.16 Clock Generation Module Characteristics for more information.
3. No more than 10% duty cycle deviation from 50%
4. Some modules may require a minimum frequency greater than dc for proper operation. See appropriate table for this in-
formation.
5. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
6. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to be recognized.
7. The minimum period, t_ILIL, should not be less than the number of cycles it takes to execute the interrupt service routine
plus t_CYC.
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor
237