MC68HC08GP32A Datasheet, PDF (176/258 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
SBSW — SIM Break Stop/Wait
1 = Wait mode was exited by break interrupt.
0 = Wait mode was not exited by break interrupt.
SBSW can be read within the break state SWI routine. The user can modify the return address on the
stack by subtracting one from it.
15.7.2 SIM Reset Status Register
This register contains six flags that show the source of the last reset provided all previous reset status bits
have been cleared. Clear the SIM reset status register by reading it. A power-on reset sets the POR bit
and clears all other bits in the register.
Address: $FE01
Bit 7
6
5
4
3
2
Read: POR
PIN
COP
ILOP
ILAD
0
Write:
Reset: 1
0
0
0
0
0
= Unimplemented
1
Bit 0
LVI
0
0
0
Figure 15-21. SIM Reset Status Register (SRSR)
POR — Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of SRSR
PIN — External Reset Bit
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
0 = POR or read of SRSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
ILAD — Illegal Address Reset Bit (opcode fetches only)
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
LVI — Low-Voltage Inhibit Reset Bit
1 = Last reset caused by the LVI circuit
0 = POR or read of SRSR
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
176
Freescale Semiconductor