MC68HC08GP32A Datasheet, PDF (174/258 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
Figure 15-16 and Figure 15-17 show the timing for WAIT recovery.
IAB
$6E0B
$6E0C $00FF $00FE $00FD $00FC
IDB $A6 $A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
Note: EXITSTOPWAIT = RST pin, CPU interrupt, or break interrupt
Figure 15-16. Wait Recovery from Interrupt or Break
IAB
$6E0B
32
CYCLES
32
CYCLES
RST VCT H RST VCT L
IDB $A6 $A6
$A6
RST
CGMXCLK
Figure 15-17. Wait Recovery from Internal Reset
15.6.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the clock generator module outputs (CGMOUT and CGMXCLK) in stop mode, stopping
the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the mask option register
(MOR). If SSREC is set, stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down
to 32. This is ideal for applications using canned oscillators that do not require long startup times from
stop mode.
NOTE
External crystal applications should use the full stop recovery time by
clearing the SSREC bit unless the OSCSTOPENB bit is set in MOR2.
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period. Figure 15-18 shows stop mode entry timing.
NOTE
To minimize stop current, all pins configured as inputs should be driven to
a 1 or 0.
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
174
Freescale Semiconductor