MC68HC08GP32A Datasheet, PDF (107/258 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 12
Input/Output (I/O) Ports
12.1 Introduction
Thirty-three (33) bidirectional input-output (I/O) pins form five parallel ports. All I/O pins are programmable
as inputs or outputs. All individual bits within port A, port C, and port D are software configurable with
pullup devices if configured as input port bits. The pullup devices are automatically and dynamically
disabled when a port bit is switched to output mode.
NOTE
Connect any unused I/O pins to an appropriate logic level, either V_DD or
V_SS. Although the I/O ports do not require termination for proper operation,
termination reduces excess current consumption and the possibility of
electrostatic damage.
Addr.
$0000
$0001
$0002
$0003
$0004
$0005
Register Name
Bit 7
6
5
4
3
Read:
Port A Data Register
(PTA) Write:
See page 110.
Reset:
PTA7
PTA6
PTA5
PTA4
PTA3
Unaffected by reset
Port B Data Register ^Read:
(PTB) Write:
See page 112. _Reset:
PTB7
PTB6
PTB5
PTB4
PTB3
Unaffected by reset
Port C Data Register ^Read:
0
(PTC) Write:
See page 114. _Reset:
PTC6
PTC5
PTC4
PTC3
Unaffected by reset
Read:
Port D Data Register
(PTD) Write:
See page 116.
Reset:
PTD7
PTD6
PTD5
PTD4
PTD3
Unaffected by reset
Data Direction Register A ^Read:
(DDRA) Write:
See page 110. _Reset:
DDRA7
0
DDRA6
0
DDRA5
0
DDRA4
0
DDRA3
0
Data Direction Register B ^Read:
(DDRB) Write:
See page 113. _Reset:
DDRB7
0
DDRB6
0
DDRB5
0
DDRB4
0
DDRB3
0
= Unimplemented
Figure 12-1. I/O Port Register Summary
2
PTA2
PTB2
PTC2
PTD2
DDRA2
0
DDRB2
0
1
PTA1
PTB1
PTC1
PTD1
DDRA1
0
DDRB1
0
Bit 0
PTA0
PTB0
PTC0
PTD0
DDRA0
0
DDRB0
0
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor
107