MC68HC08GP32A Datasheet, PDF (103/258 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 11
Mask Option Registers (MOR2 and MOR1)
11.1 Introduction
The two mask option registers at $001E and $001F (see Figure 11-1 and Figure 11-2) are read-only
registers. They are defined by mask options (hard-wired connections) specified at the same time as the
read-only memory (ROM) code submission.
11.2 Mask Option Registers
Address:
Read:
Write:
Reset:
$001E
Bit 7
0
6
5
4
3
2
1
0
0
0
0
TBMCLK-
SEL
OSCS-
TOPENB
Mask defined
= Unimplemented
Figure 11-1. Mask Option Register 2 (MOR2)
Bit 0
SCIBDSRC
TBMCLKSEL — Timebase Clock Select Bit
TBMCLKSEL enables an enable of the extra divide-by-128 prescaler in the timebase module. Setting
this bit enables the extra prescaler and clearing this bit disables it. Refer to Table 17-1. Timebase
Divider Selection for timebase divider selection details
1 = Enables extra divide-by-128 prescaler in timebase module
0 = Disables extra divide-by-128 prescaler in timebase module
OSCSTOPENB— Oscillator Stop Mode Enable Bar Bit
OSCSTOPENB enables the oscillator to continue operating during stop mode. Setting the
OSCSTOPENB bit allows the oscillator to operate continuously even during stop mode. This is useful
for driving the timebase module to allow it to generate periodic wakeup while in stop mode. (See 9.5
Clock Generator Module (CGM) subsection 9.5.2 Stop Mode.)
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode
SCIBDSRC — SCI Baud Rate Clock Source Bit
SCIBDSRC controls the clock source used for the SCI. The setting of this bit affects the frequency at
which the SCI operates.
1 = Internal data bus clock used as clock source for SCI
0 = External oscillator used as clock source for SCI
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor
103