MC68HC08GP32A Datasheet, PDF (201/258 Pages) Freescale Semiconductor, Inc – Microcontrollers

TBM Interrupt Rate
17.5 TBM Interrupt Rate
The interrupt rate is determined by the equation:
t_TBMRATE =
Divider
f_CGMXCLK
where:
f_CGMXCLK = Frequency supplied from the clock generator (CGM) module
Divider = Divider value as determined by TBR2–TBR0 settings and TBMCLKSEL, see Table 17-1
Table 17-1. Timebase Divider Selection
TBR2
0
0
0
0
1
1
1
1
TBR1
0
0
1
1
0
0
1
1
TBR0
0
1
0
1
0
1
0
1
Divider Tap
TBMCLKSEL
0
1
32,768
4,194,304
8192
1,048,576
2048
262144
128
16,384
64
8192
32
4096
16
2048
8
1024
As an example, a clock source of 32.768 kHz, with the TBMCLKSEL set for divide-by-128 and
TBR2–TBR0 set to {101}, the divider tap is 1 and the interrupt rate calculates to:
4096/32,768 = 125 ms
NOTE
Do not change TBR2–TBR0 bits while the timebase is enabled (TBON = 1).
17.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
17.6.1 Wait Mode
The timebase module remains active after execution of the WAIT instruction. In wait mode the timebase
register is not accessible by the CPU.
If the timebase functions are not required during wait mode, reduce the power consumption by stopping
the timebase before executing the WAIT instruction.
17.6.2 Stop Mode
The timebase module may remain active after execution of the STOP instruction if the internal clock
generator has been enabled to operate during stop mode through the OSCSTOPENB bit in the mask
option register. The timebase module can be used in this mode to generate a periodic wakeup from stop
mode.
MC68HC08GP32A • MC68HC08GP16A Data Sheet, Rev. 1.0
Freescale Semiconductor
201