MC68HC05P18 Datasheet, PDF (99/144 Pages) Freescale Semiconductor, Inc – Advance Information

Freescale Semiconductor, Inc.
Advance Information — MC68HC05P18/MC68HC805P18
Section 11. Serial Input/Output Port (SIOP)
11.1 Contents
11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
11.3 SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
11.3.1 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
11.3.2 Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
11.3.3 Serial Data Output (SDO). . . . . . . . . . . . . . . . . . . . . . . . . .102
11.4 SIOP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
11.4.1 SIOP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
11.4.2 SIOP Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
11.4.3 SIOP Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
11.2 Introduction
The simple synchronous serial input/output port (SIOP) subsystem is
designed to provide efficient serial communications between peripheral
devices or other MCUs. The SIOP is implemented as a 3-wire
master/slave system with serial clock (SCK), serial data Input (SDI), and
serial data output (SDO). A block diagram of the SIOP is shown in
Figure 11-1.
The SIOP subsystem shares its input/output pins with port B. When the
SIOP is enabled (SPE bit set in register SCR), port B data direction
registers (DDR) and data registers are modified by the SIOP. Although
port B DDR and data registers can be altered by application software,
these actions could affect the transmitted or received data.
MC68HC(8)05P18 — Rev. 2.0
MOTOROLA
Serial Input/Output Port (SIOP)
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