MC68HC05P18 Datasheet, PDF (42/144 Pages) Freescale Semiconductor, Inc – Advance Information

Interrupts
Freescale Semiconductor, Inc.
When the current instruction is completed, the processor checks all
pending hardware interrupts. If interrupts are not masked (I bit in the
condition code register is clear) and the corresponding interrupt enable
bit is set, the processor proceeds with interrupt processing. Otherwise,
the next instruction is fetched and executed. The software interrupt
(SWI) is executed the same as any other instruction, regardless of the I
bit state.
When an interrupt is to be processed, the CPU puts the register contents
on the stack, sets the I bit in the CCR, and fetches the address of the
corresponding interrupt service routine from the vector table at locations
$3FF0–$3FFF. If more than one interrupt is pending when the interrupt
vector is fetched, the interrupt with the highest vector location shown in
Table 4-1 will be serviced first.
An return-from-interrupt (RTI) instruction is used to signify when the
interrupt software service routine is completed. The RTI instruction
causes the CPU state to be recovered from the stack and normal
processing to resume at the next instruction that was to be executed
when the interrupt took place.
Figure 4-1 shows the sequence of events that occurs during interrupt
processing.
Table 4-1. Vector Addresses for Interrupts and Reset
Register
N/A
N/A
N/A
TSR
TSR
TSR
N/A
N/A
N/A
N/A
Flag
Name
N/A
N/A
N/A
ICF
OCF
TOF
N/A
N/A
N/A
N/A
Interrupts
Reset
Software
External interrupt
Timer input capture
Timer output compare
Timer overflow
Unimplemented
Unimplemented
Unimplemented
Unimplemented
CPU
Interrupt
RESET
SWI
IRQ
TIMER
TIMER
TIMER
N/A
N/A
N/A
N/A
Vector
Address
$3FF3–$3FFF
$3FFC–$3FFD
$3FFA–$3FFB
$3FF8–$3FF9
$3FF8–$3FF9
$3FF8–$3FF9
$3FF6–$3FF7
$3FF4–$3FF5
$3FF2–$3FF3
$3FF0–$3FF1
Advance Information
42
MC68HC(8)05P18 — Rev. 2.0
Interrupts
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